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IS25WQ080 integrated silicon solution, inc.- www.issi.com rev. a 09/18/2012 1 features ? single power supply operation - low voltage range: 1.65 v ? 2 v ? memory organization - IS25WQ080: 1024k x 8 (8 mbit) ? cost effective sector/block architecture - 8mb : uniform 4kbyte sectors / sixteen uniform 64kbyte blocks ? serial peripheral interface (spi) compatible - supports single-, dual- or quad-output - supports spi modes 0 and 3 - maximum 33 mhz clock rate for normal read - maximum 104 mhz clock rate for fast read - maximum 208mhz clock rate equivalent dual spi - maximum 416mhz clock rate equivalent quad spi ? byte program operation - typical 8 us/byte ? page program (up to 256 bytes) operation - maximum 0.7 ms per page program ? sector, block or chip erase operation - sector erase (4kb) ? 150 ms (max) - block erase ? (32k/64kb) ? 0.5s (max) - chip erase ? 6s (8mb) (max) ? deep power-down mode 1ua (typ) ? low power consumption - max 15 ma active read current - max 20 ma program/erase current - max 50ua standby current ? hardware write protection - protect and unprotect the device from write operation by write protect (wp#) pin ? software write protection - the block protect (bp3, bp2, bp1, bp0) bits allow partial or entire memory to be configured as read-only ? high product endurance - guaranteed 100,000 program/erase cycles per single sector - minimum 20 years data retention ? industrial standard pin-out and package - 8-pin pdip - 8-pin 208mil soic - 8-pin 150mil soic - 8-pin 150mil vvsop - 8-contact wson - 16-pin 300mil sop - lead-free (pb-free) package additional 256-byte security information one-time programmable (otp) area general description the IS25WQ080 are 8mbit serial peripheral interface ( spi) flash memories, providing single-, dual or quad- output. the devices are designed to support a 33 mhz fclock rate in normal read mode, and 104 mhz in fast read, the fastest in the industry. the devices use a si ngle low voltage power supply, ranging from 1.65 volt to 2.0 volt, to perform read, erase and program operations. the devices can be programmed in standard eprom programmers. the IS25WQ080 are accessed through a 4-wi re spi interface consisting of serial data input/output (sl), serial data output (so), serial clock (sck), and chip enable (ce#) pins. the devices support page program mode, where 1 to 256 bytes data can be programmed into t he memory in one program operation. these devices are divided into uniform 4 kbyte sectors or uniform 64 kbyte blocks. the IS25WQ080 are manufactured on pflash??s advanced non-volatile technology. the devices are offered in 8-pin soic 150mil/208mil, 8-contact wson, 8-pin pdip and 8-pin vvsop 150mil, . 8 mbit bit single operating vo ltage serial flash memory with 104 mhz dual- or quad -output spi bus interface preliminary datasheet
IS25WQ080 integrated silicon solution, inc.- www.issi.com rev. a 09/18/2012 2 connection diagrams 5 6 7 8 1 2 3 4 vcc nc(io3) sck si(io0) so(io1) gnd wp#(io2) ce# 16-pin soic ce# ce# gnd vcc hold# (io3) sck si (io0 ) si (io0 ) sck hold# (io3) vcc so (io1) wp# (io2) gnd 1 2 3 4 8 7 6 5 1 2 3 4 8 7 6 5 8-contact wson wp# (io2) so (io1) 8-pin soic/vvsop 8-pin pdip hold#(io3)
IS25WQ080 integrated silicon solution, inc.- www.issi.com rev. a 09/18/2012 3 pin descriptions symbol type description ce# input chip enable: ce# low activates the devices internal circuitries for device operation. ce# high deselects the devices and switches into standby mode to reduce the power consumption. when a device is not selected, data will not be accepted via the serial input pin (sl), and the serial output pin (so) will rema in in a high impedance state. sck input serial data clock si (io0) input/output serial data input/output so (io1) input/output serial data input/output gnd ground vcc device power supply wp# (io2) input/output write protect/serial data outpu t: a hardware program/erase protection for all or part of a memory array. when the wp# pi n is low, memory array write-protection depends on the setting of bp3, bp2, bp1 and bp0 bits in the status register. when the wp# is high, the status register are not write-protected. when the qe bit of is set ??1??, the /w p pin (hardware write protect) function is not available since this pin is used for io2 hold# (io3) input/output hold: pause serial communication by the master device without resetting the serial sequence. when the qe bit of status register-2 is set for ??1??, the function is serial data input & output (for 4xi/o read mode)
IS25WQ080 integrated silicon solution, inc.- www.issi.com rev. a 09/18/2012 4 block diagram si ( io0 ) wp# (io2) hold# (io3) so (io1)
IS25WQ080 integrated silicon solution, inc.- www.issi.com rev. a 09/18/2012 5 spi modes description multiple IS25WQ080 devices can be connected on the spi serial bus and controlled by a spi master, i.e. microcontroller, as shown in figure 1. the devices support either of two spi modes: mode 0 (0, 0) mode 3 (1, 1) the difference between these two modes is the clock polarity when the spi master is in stand-by mode: the serial clock remains at ?0? (sck = 0) for mode 0 and the clock remains at ?1? (sck = 1) for mode 3. please refer to figure 2. for both modes, the input data is latched on the rising edge of serial clock (sck), and the output data is available from the falling edge of sck. figure 1. connection diagram among spi master and spi slaves (memory devices) figure 2. spi modes supported msb msb sck sck so si in p ut mode mode 0 ( 0 , 0 ) mode 3 ( 1 , 1 ) spi master (i.e. microcontroller) cs3 cs2 cs1 spi memory device spi memory devic e spi memory device spi interface with (0,0) or (1,1) sdi sdi sck sck sck sck so so so si si si ce# ce# ce# wp# wp# wp# hold# hold# hold# n ote : 1. th e wri te pr otect ( wp #) a n d h o l d ( h o ld #) s i g n a l s s h ou l d be d riv e n hi g h o r l o w as
IS25WQ080 integrated silicon solution, inc.- www.issi.com rev. a 09/18/2012 6 system configuration the IS25WQ080 devices are designed to interface directly with the synchr onous serial peripheral interface (spi) of the motorola mc68hcxx series of microcontrollers or any spi interface-equipped system controllers. the devices have the superset features that can be enabled through specific software instructions: configurable sector size: the memory array of IS25WQ080 is divided into uniform 4 kbyte sectors or uniform 32k/64 kbyte blocks (a block consists of sixteen adjacent sectors). the below table 1 illustrates the memory map of the devices. block/sector addresses table 1. block/sector addresses of IS25WQ080 memory density block no.(64kb) block no.(32kb) sector no. sector size (kbytes) address range 16 mbit 8 mbit block 0 block 0 sector 0 4 000000h ? 000fffh : : 001000h ? 001fffh block 1 : : : sector 15 4 00f000h ? 00ffffh block 1 block 2 sector 16 4 010000h ? 010fffh : : 011000h ? 011fffh block 3 : : : sector 31 4 01f000h ? 01ffffh : : : : : block 7 : : : 070000h ? 07ffffh block 8 : sector 128 4 080000h ? 08ffffh : : : : : : : : : : block 15 block30 : sector 255 : 4 0f0000h ? 0fffffh block31 block 16 block32 sector 256 : 4 : 100000h ? 10ffffh block33 : : : : : : : : : : block 31 block62 : sector511 4 1f0000h ? 1fffffh block63
IS25WQ080 integrated silicon solution, inc.- www.issi.com rev. a 09/18/2012 7 registers (continued) status register refer to tables 2 and 5 for status register format and status register bit definitions. the bp0, bp1, bp2, bp3 and srwd are non-volatile memory cells that can be wr itten by a write status register (wrsr) instructio n. the default value of the bp2, bp1, bp0, and srwd bits were set to ?0? at factory. the status register can be read by the read status register (rdsr). refer to table 10 for instruction set. the function of status register bits are described as follows: wip bit : the write in progress (wip) bit is read-only, and can be used to detect the progress or completion of a program or erase operation. when the wip bit is ?0?, the device is ready fo r a write status register, program or erase operation. when the wip bit is ?1?, the device is busy. wel bit : the write enable latch (wel) bit indicates the status of the internal write enable latch. when the wel is ?0?, the write enable latch is disabled, and all write operations, including wr ite status register, write configuration register, page program, sector erase, block and chip erase operations are inhibited. when the wel bit is ?1?, write operations are allowed. the wel bit is set by a write enable (wren) instruction. each write register, program and erase instruction must be preceded by a wren instruction. the wel bit can be reset by a write disable (wrdi) instruction. it will automatically be the reset after the completion of a write instruction. bp3, bp2, bp1, bp0 bits : the block protection (bp3, bp2, bp1 and bp0) bits are used to define the portion of the memory area to be protected. refer to tables 6 and 7 for the block write protection bit settings. when a defined combination of bp3, bp2, bp1 and bp0 bits are set, the corresponding memory area is protected. any program or erase operation to that area will be inhibited.note: a chip eras e (chip_er) instruction is executed only if all the block protection bits are set as ?0?s. srwd bit : the status register write disable (srwd) bits operates in conjunction with the write protection (wp#) signal to provide a hardware protection mode. when the srwd is set to ?0?, the status register is not write-protected. when t he srwd is set to ?1? and the wp# is pulled low (v il ), the bits of status register (srwd, bp3, bp2, bp1, bp0) become read-only, and a wrsr instruction will be ignored. if the srwd is set to ?1? and wp# is pulled high (v ih ), the status register can be changed by a wrsr instruction. qe bit : the quad enable (qe) is a non-volatile bit in the status register that allows quad operation. when the qe bit is set to ?0?,the pin wp# and hold# are enable. when the qe bit is set to ?1?, the pin io2 and io3 are enable. warning: the qe bit should never be set to a 1 during standard spi or dual spi operation if the wp# or hold# pins are tied directly to the power supply or ground. table 2. status register format bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 srwd qe bp3 bp2 bp1 bp0 wel wip default (flash bit) 0 0 0 0 0 0 0 0 ? the default value of the bp3, bp2, bp1, bp0, and sr wd bits were set to ?0? at factory.
IS25WQ080 integrated silicon solution, inc.- www.issi.com rev. a 09/18/2012 8 registers (continued) function register the function register can be read by the read function register (rfr). refer to table 9 for instruction set. the function of function register bits are described as follows: esus bit: the erase suspend status indicates when an erase operation has been suspended. the esus bit is ?1? after the host issues a suspend command during an erase operation. once the suspended erase resumes, the esus bit is reset to ?0.? psus bit: the program suspend status bit indicates when a program operation has been suspended. the psus is ?1? after the host issues a suspend command during the program operation. once the suspended program resumes, the psus bit is reset to ?0.? table 3. function register format bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 x x x x x psus esus x default 0 0 0 0 0 0 0 0 table 4. function register bit definition bit name definition read- /write non-volatile bit bit 1 esus erase suspend bit: ?0? indicates erase is not suspend ?1? indicates erase is suspend r no bit 2 psus program suspend bit: ?0? indicates program is not suspend ?1? indicates program is suspend r no
IS25WQ080 integrated silicon solution, inc.- www.issi.com rev. a 09/18/2012 9 registers (continued) table 5. status regi ster bit definition bit name definition read- /write non-volatile bit bit 0 wip write in progress bit: ?0? indicates the device is ready ?1? indicates a write cycle is in progress and the device is busy r no bit 1 wel write enable latch: ?0? indicates the device is not write enabled (default) ?1? indicates the device is write enabled r/w no bit 2 bp0 block protection bit: (see tables 6 and 7 for details) ?0? indicates the specific blocks are not write-protected (default) ?1? indicates the specific blocks are write-protected r/w yes bit 3 bp1 bit 4 bp2 bit 5 bp3 bit 6 qe quad enable bit: ?0? indicates the quad output function disable (default) ?1? indicates the quad output function enable r/w yes bit 7 srwd status register write disable: (see table 10 for details) ?0? indicates the status register is not write-protected (default) ?1? indicates the status register is write-protected r/w yes table 7. block write protect bits for IS25WQ080 status register bits protected memory area bp3 bp2 bp1 bp0 8 mbit 0 0 0 0 none 0 0 0 1 upper sixteenth (1 block : 15 th ): 0 0 1 0 upper eighth (2 blocks :14 th and 15 th ): 0 0 1 1 upper quarter (4 blocks :12 th to 15 th ): 0 1 0 0 upper half (8 blocks :8 th to 15 th ): 0 1 0 1 all blocks (16blocks : 0 to 15): 000000h ? 0fffffh 0 1 1 0 0 1 1 1 1 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 (8blocks :0 th to 7 th ): 1 1 0 0 (4 blocks :0 th to 3th): 1 1 0 1 (2blocks :0 th to 1th): 1 1 1 0 (1 blocks :0 th ): 1 1 1 1 none
IS25WQ080 integrated silicon solution, inc.- www.issi.com rev. a 09/18/2012 10 registers (continued) protection mode the IS25WQ080 have two types of write-protection mechanisms: hardware and software. these are used to prevent irrelevant operation in a possibly noisy environment and prot ect the data integrity. hardware writ e-protection the devices provide two ha rdware write-protection features: a. when inputting a program, erase or write status register instruction, the number of clock pulse is checked to determine whether it is a multiple of eight before the executing. any incomplete instruction command sequence will be ignored. b. write inhibit is 1.3v, all write sequence will be ignored when vcc drop to 1.3v and lower. c. the write protection (wp#) pin provides a hardware write protection method for bp3, bp2, bp1, bp0 and srwd in the status register. refer to the status register description. software write protection the IS25WQ080 also provides two software write protection features: a. before the execution of any program, erase or write status register inst ruction, the write enable latch (wel) bit must be enabled by executing a write enable (wren) instruction. if the wel bit is not enabled first, the program, erase or write register instruction will be ignored. b. the block protection (bp3, bp2, bp1, bp0) bits allow part or the whole memory area to be write- protected. table 8. hardware write protection on status register srwd wp# status register 0 low writable 1 low protected 0 high writable 1 high writable device operation the IS25WQ080 utilize an 8-bit instruction register. refer to table 9 instruction set for details of the instructions and instruction codes. all instructions, addresses, and data are shi fted in with the most significant bit (msb) first on serial data input (si). the input data on si is latched on the rising edge of serial clock (sck) after chip enable (ce#) is driven low (v il ). every instruction sequence starts with a one-byte instruction code and is followe d by address bytes, data bytes, or both address bytes and data bytes, depending on the type of instruction. ce# must be driven high (v ih ) after the last bit of the instruction sequence has been shifted in. the timing for each instruct ion is illustrated in the following operational descriptions.
IS25WQ080 integrated silicon solution, inc.- www.issi.com rev. a 09/18/2012 11 table 9. instruction set instruction name hex code operation comman d cycle maximum frequency rdid abh read manufacturer and product id/ release deep power down mode 4 bytes 104 mhz jedec id read 9fh read manufacturer and product id by jedec id command 1 byte 104 mhz rdmdid 90h read manufacturer and device id 4 bytes 104 mhz wren 06h write enable 1 byte 104 mhz wrdi 04h write disable 1 byte 104 mhz rdsr 05h read status register 1 byte 104 mhz wrsr 01h write status register 2 bytes 104 mhz read 03h read data bytes from memo ry at normal read mode 4 bytes 33 mhz fast_read 0bh read data bytes from memory at fast read mode 5 bytes 104 mhz frdo 3bh fast read dual output 5 bytes 104 mhz frdio bbh fast read dual i/o 3 bytes 104mhz frqo 6bh fast read quad output 5 bytes 104 mhz frqio ebh fast read quad i/o 2 bytes 104mhz mr ffh mode reset 2 byte 104mhz page_ prog 02h page program data bytes into memory 4 bytes + 256b 104 mhz sector_er d7h/ 20h sector erase 4 bytes 104 mhz block_er (32kb) 52h block erase 4 bytes 104 mhz block_er (64kb) d8h block erase 4 bytes 104 mhz chip_er c7h/ 60h chip erase 1 byte 104 mhz dual page program a2h page program data bytes into memory with dual interface 104mhz quad page program 32h page program data bytes into memory with quad interface 4 bytes + 256b 104mhz power down b9h 104mhz program information raw b1h program 256 bytes of security area 4 bytes 104 mhz read information raw 4bh read 256 bytes of security area 4 bytes 33 mhz program/erase suspend 75h/ b0h suspend during the program/erase 1 byte 104mhz program/erase resume 7ah/ 30h resume program/erase 1 byte 104mhz rdfr 07h read function register 1 byte 104mhz hold operation hold# is used in conjunction with ce# to select the IS25WQ080. when the devices are selected and a serial sequence is underway, hold# can be used to pause the serial communication with the master device without resetting the serial sequence. to pause, hold# is brought low while the sck signal is low. to resume serial communication, hold# is brought high while the sck signal is low (sck may still toggle during hold). inputs to sl will be ignored while so is in the high impedance state.
IS25WQ080 integrated silicon solution, inc.- www.issi.com rev. a 09/18/2012 12 device operation (continued) rdid command (read product identification)/ release power-down operation the release from power-down or high performance mode / device id instruction is a multi-purpose instruction. the read product identification (rdid) instruction is for reading out the old style of 8-bit electronic signature, whose values are shown as table 10 of id definitions. this is not same as rdid or jedec id instruction. it?s not recommended to use for new design. for new design, please use rdid or jedec id instruction. the rdes instruction code is followed by three dummy bytes, each bit being latched-in on si during the rising edge of sck. then the device id is shifted out on so with the msb first, each bit been shifted out during the falling edge of sck. the rdes instruction is ended by ce# goes high. the device id outputs repeatedly if continuously send the additional clock cycles on sck while ce# is at low. to release the device from the power-down state mode, the instruction is issued by driving the ce# pin low, shifting the instruction code ??abh?? and driving ce# high as shown in figure 3. release from power-down will take the time duration of t res1 before the device will resume normal operation and other instructions are ac cepted. the ce# pin must remain high during the t res1 time duration. if the release from power-down / rdid instruction is issued while an erase, program or write cycle is in process (when wip equals 1) the instruction is ignored and will not have any effects on the current cycle table 10. product identification product identification data manufacturer id first byte 9dh second byte 7fh device id: device id1 device id2 IS25WQ080 13h 54h figure 3. read product identification sequence 01 8 31 38 39 46 47 54 high impedance device id1 device id1 device id1 sck ce# si so instruction 9 7 1010 1011b 3 dummy bytes
IS25WQ080 integrated silicon solution, inc.- www.issi.com rev. a 09/18/2012 13 device operation (continued) jedec id read command (read product identification by jedec id) operation the jedec id read instruction allows the user to read the manufacturer and product id of devices. refer to table 10 product identification for pflash manufacturer id and device id. after the jedec id read command is input, the second manufacturer id (7fh) is shifted out on so with the msb first, followed by the first manufacturer id (9dh) and the device id2 (54h, in the case of the IS25WQ080), each bit shifted out during the falling edge of sck. if ce# stays low after the last bit of the device id is shifted out, the manufacturer id and device id will loop until ce# is pulled high. figure 4. read product identification by jedec id read sequence sck ce# si instruction 1001 1111b 0 8 15 23 24 31 7 16 high impedance so device id2 manufacture id1 manufacture id2
IS25WQ080 integrated silicon solution, inc.- www.issi.com rev. a 09/18/2012 14 device operation (continued) rdmdid command (read device manufacturer and device id) operation the read product identificat ion (rdid) instruction allows the user to read the manufacturer and product id of the devices. refer to table 10 product identification for pflash? manufacturer id and device id. the rdid instruction code is followed by two dummy bytes and one byte address (a7~a0), each bit being latched-in on si during the rising edge of sck. if one byte address is initially set to a0 = 0, then the first manufacturer id (9dh) is shifted out on so with the msb first, the device id1 and the second manufacturer id (7fh), each bit been shifted out during the falling edge of sck. if one byte address is initially set to a0 = 1, then device id1 will be read first, then followed by the first manufacture id (9dh) and then second manufacture id (7fh). the manufacture and device id can be read continuously, alternating from one to the others. the instruction is completed by driving ce# high. figure 5. read product identification by rdmdid read sequence
IS25WQ080 integrated silicon solution, inc.- www.issi.com rev. a 09/18/2012 15 note : 1. address a0 = 0, will output the 1 st manufacture id (9dh) fi rst -> device id1 -> 2 nd manufacture id (7fh) address a0 = 1, will output the device id1 -> 1 st manufacture id (9d) -> 2 nd manufacture id (7fh)
IS25WQ080 integrated silicon solution, inc.- www.issi.com rev. a 09/18/2012 16 device operation (continued) write enable operation the write enable (wren) instruction is used to set the write enable latch (wel) bit. the wel bit of the IS25WQ080 is reset to the write ?protected state after power-up. the wel bit must be write enabled before any write operation, including sector, block erase, chip erase, page program and write status register. the wel bit will be reset to the write-protect state automatically upon completi on of a write operation. the wren instruction is required before any above operation is executed. figure 6. write enable sequence wrdi command (write disable) operation the write disable (wrdi) instruction resets the wel bit and disables all write instructions. the wrdi instruction is not required a fter the execution of a write instruction, since the wel bi t is automatically reset. figure 7. write disable sequence
IS25WQ080 integrated silicon solution, inc.- www.issi.com rev. a 09/18/2012 17 device operation (continued ) rdsr command (read status register) operation the read status register ( rdsr) instruction provides access to the status register. during the execution of a program, erase or write status register operation, all other instructions will be ignored except the rdsr instruction, which can be used to check the progress or completion of an operation by reading the wip bit of status register. figure 8. read status register sequence wrsr command (write status register) operation the write status register (wrsr) instruction allows the user to enable or disable the block protection and status register write protecti on features by writing ?0?s or ?1?s into the non-volatile bp3, bp2, bp1, bp0 and srwd bits. figure 9. write status register sequence
IS25WQ080 integrated silicon solution, inc.- www.issi.com rev. a 09/18/2012 18 device operation (continued) read command (read data) operation the read data (read) instruction is used to read memory data of a IS25WQ080 under normal mode running up to 33 mhz. the read instruction code is transmitted via the sl line, followed by three address bytes (a23 ? a0) of the first memory location to be read. a total of 24 address bits are shifted in, but only a ms (most significant address) ? a0 are decoded. the remaining bits (a23 ? a ms ) are ignored. the first byte addressed can be at any memory location. upon completion, any data on the sl will be ignored. refer to table 11 for the related address key. the first byte data (d7 ? d0) addressed is then shifted out on the so line, msb first. a single byte of data, or up to the whole memory array, can be read out in one read instruction. the address is automatically incremented after each byte of data is shifted out. the read operation can be terminated at any time by driving ce# high (v ih ) after the data comes out. when the highest address of the devices is reached, the address counter will roll over to the 000000h address, allowing the entire memory to be read in one continuous read instruction. if a read data instruction is issued while an erase, program or write cycle is in process (wip=1) the instruction is ignored and will not have any effects on the current cycle table 11. address key address IS25WQ080 a n ( a ms ? a 0) a19 ? a0 don?t care bits a23 ? a20 figure 10. read data sequence
IS25WQ080 integrated silicon solution, inc.- www.issi.com rev. a 09/18/2012 19 device operation (continued) fast_read command (fast read data) operation the fast_read instruction is used to read memory data at up to a 104 mhz clock. the fast_read instruction code is followed by three address bytes (a23 ? a0) and a dummy byte (8 clocks), transmitted via the si line, with each bit latched-in during the rising edge of sck. then the first data byte addressed is shifted out on the so line, with each bit shifted out at a maximum frequency f ct , during the falling edge of sck. the first byte addressed can be at any memory location. the address is automatically incremented after each byte of data is shifted out. when the highest address is reached, the address counter will roll over to the 000000h address, allowing the entire memory to be read with a single fast_read instruction. the fast_read instruction is terminated by driving ce# high (v ih ). if a fast read data instruction is issued while an erase, program or write cycle is in process (wip=1) the instruction is ignored and will not have any effects on the current cycle figure 11. fast read data sequence sio
IS25WQ080 integrated silicon solution, inc.- www.issi.com rev. a 09/18/2012 20 device operation (continued ) frdo command (fast read dual output) operation the frdo instruction is used to read memory data on two output pins each at up to a 104 mhz clock. the frdo instruction code is followed by three address bytes (a23 ? a0) and a dummy byte (8 clocks), transmitted via the si line, with each bit latched-in during the rising edge of sck. then the first data byte addressed is shifted out on the so and sio lines, with each pair of bits shifted out at a maximum frequency f ct , during the falling edge of sck. the first bit (msb) is output on so, while simultaneously the second bit is output on sio. the first byte addressed can be at any memory location. the address is automatically incremented after each byte of data is shifted out. when the highest address is reached, the address counter will roll over to the 000000h address, allowing the entire memory to be read with a single frdo inst ruction. frdo instruction is terminated by driving ce# high (v ih ). if a frdo instruction is issued while an erase, program or write cycle is in process (wip=1) the instruction is ignored and will not have any effects on the current cycle figure 12. fast read dual-output sequence
IS25WQ080 integrated silicon solution, inc.- www.issi.com rev. a 09/18/2012 21 device operation (continued ) frdio command (fast read dual i/o) operation the frdio instruction is similar to the frdo instruction, but allows the address bits to be input two bits at a time. this may allow for code to be executed directly from the spi in some applications. the frdio instruction code is followed by three address bytes (a23 ? a0) and a mode byte, transmitted via the io0 and io1 lines, with each pair of bits latched-in during the rising edge of sck. the address msb is input on io1, the next bit on io0, and continues to shift in alternating on the two lines. the mode byte contains the value ax, where x is a ?don?t care? value. then the first data byte addressed is shifted out on the io1 and io0 lines, with each pair of bits shifted out at a maximum frequency f ct , during the falling edge of sck. the msb is output on io1, while simultaneously the second bit is output on io0. figure 13 illustrates the timing sequence. the first byte addressed can be at any memory location. the address is automatically incremented after each byte of data is shifted out. when the highest address is reached, the address counter will roll over to the 000000h address, allowing the entire memory to be read with a single frdi o instruction. frdio instruction is terminated by driving ce# high (v ih ). the device expects the next operation will be another frdio. it remains in this mode until it receives a mode reset (ffh) command. in subsequent frdio execution, the command code is not input, saving timing cycles as described in figure 14. if a frdio instruction is issued while an erase, program or write cycle is in process (wip=1) the instruction is ignored and will not have any effects on the current cycle figure 13. fast read dual i/o sequence (with command decode cycles)
IS25WQ080 integrated silicon solution, inc.- www.issi.com rev. a 09/18/2012 22 device operation (continued ) figure 14. fast read dual i/o sequence (without command decode cycles) frqo command (fast read quad output) operation the frqo instruction is used to read memory data on four output pins each at up to a 104 mhz clock. the frqo instruction code is followed by three address bytes (a23 ? a0) and a dummy byte (8 clocks), transmitted via the si line, with each bit latched-in during the rising edge of sck. then the first data byte addressed is shifted out on the io3, io2, io1 and io0 lines, with each group of four bits shifted out at a maximum frequency f ct , during the falling edge of sck. the first bit (msb) is output on io3, while simultaneously the second bit is output on io2, the third bit is output on io1, etc. the first byte addressed can be at any memory location. the address is automatically incremented after each byte of data is shifted out. when the highest address is reached, the address counter will roll over to the 000000h address, allowing the entire memory to be read with a single frqo inst ruction. frqo instruction is terminated by driving ce# high (v ih ). if a frqo instruction is issued while an erase, program or write cycle is in process (wip=1) the instruction is ignored and will not have any effects on the current cycle
IS25WQ080 integrated silicon solution, inc.- www.issi.com rev. a 09/18/2012 23 device operation (continued ) figure 15. fast read quad-output sequence r 0 1 2345 67 8 9 10 11 28 29 30 31 ... instruction = 0110 1011b ... 23 22 21 3 2 1 0 3 - byte address ce# sck si so high impedance 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 5 4 1 0 5 4 1 0 5 4 1 0 5 4 1 0 5 4 ce# sck io0 io1 high impedance data out 1 data out 2 7 6 3 2 7 6 3 2 7 6 3 2 7 6 3 2 7 6 high impedance io2 io3 data out n . . . high impedance high impedance io switch from input to output 8 dummy clocks
IS25WQ080 integrated silicon solution, inc.- www.issi.com rev. a 09/18/2012 24 device operation (continued ) frqio command (fast read quad i/o) operation the frqio instruction is similar to the frqo instruction, but allows the address bits to be input four bits at a time. this may allow for code to be executed directly from the spi in some applications. the frqio instruction code is followed by three address bytes (a23 ? a0) and a mode byte, transmitted via the io3, io2, io0 and io1 lines, with each group of four bits latched-in during the rising edge of sck. the address msb is input on io3, the next bit on io2, the next bit on io1, the next bit on io0, and continue to shift in alternating on the four. the mode byte contains the value ax, where x is a ?don?t care? value. after four dummy clocks, the first data byte addressed is shifted out on the io3, io2, io1 and io0 lines, with each group of four bits shifted out at a maximum frequency f ct , during the falling edge of sck. the first bit (msb) is output on io3, while simultaneously the second bit is output on io2, the third bit is output on io1, etc. figure 16 illustrates the timing sequence. the first byte addressed can be at any memory location. the address is automatically incremented after each byte of data is shifted out. when the highest address is reached, the address counter will roll over to the 000000h address, allowing the entire memory to be read with a single frqio instruction. frqio instruction is terminated by driving ce# high (v ih ). the device expects the next operation will be another frqio. it remains in this mode until it receives a mode reset (ffh) command. in subsequent frqio execution, the command code is not input, saving cycles as described in figure 17. if a frqio instruction is issued while an erase, program or write cycle is in process (wip=1) the instruction is ignored and will not have any effects on the current cycle
IS25WQ080 integrated silicon solution, inc.- www.issi.com rev. a 09/18/2012 25 figure 16. fast read quad i/o sequence (with command decode cycles) 0 1 2345 67 8 9 10 11 12 13 14 15 instruction = 1110 1011b 21 17 16 4 0 4 3 - byte address ce# sck io0 16 17 18 19 20 21 22 23 24 25 1 0 5 4 1 0 5 4 1 0 5 4 1 0 5 4 ce# sck io0 io1 data out 1 20 13 5 1 5 io1 12 mode bits 5 4 22 18 14 6 2 6 23 19 15 7 3 7 io2 io3 11 10 9 8 3 2 7 6 3 2 7 6 3 2 7 6 3 2 7 6 7 6 io2 io3 data out 2 data out 3 data out 4 4 dummy cycles 26 27 io switch from input to output
IS25WQ080 integrated silicon solution, inc.- www.issi.com rev. a 09/18/2012 26 device operation (continued ) figure 17. fast read quad i/o sequence (without command decode cycles) mr command (mode reset) operation the mode reset command is used to conclude subsequent frdio and frqio operations. it resets the mode bits to a value that is not ax. it should be executed after an frdio or frqio operation, and is recommended also as the first command after a system reset. the timing sequence is different depending whether the mr command is used after an frdio or frqio, as shown in figure 18.
IS25WQ080 integrated silicon solution, inc.- www.issi.com rev. a 09/18/2012 27 figure 18, mode reset command
IS25WQ080 integrated silicon solution, inc.- www.issi.com rev. a 09/18/2012 28 device operation (continued ) page_prog command (page program) operation the page program (page_prog) instruction allows up to 256 bytes data to be programmed into memory in a single operation. the destination of the memory to be programmed must be outside the protected memory area set by the block protection (bp2, bp1, bp0) bits. a page_prog instruction whic h attempts to program into a page that is write-protected will be ignored. before the execution of page_prog instruction, the write enable latch (wel) must be enabled through a write enable (wren) instruction. the page_prog instruction code, three address bytes and program data (1 to 256 bytes) are input via the sl line. program operation will start immediately after the ce# is brought high, otherwise the page_prog instruction will not be executed. the internal control logic automatically handles the programming voltages and timing. during a program operation, all instructions will be ignored except the rdsr instruction. the progress or completion of the program operation can be determined by reading the wip bit in status register via a rdsr instruction. if the wip bit is ?1?, the pr ogram operation is still in progress. if wip bit is ?0?, the program operation has completed. if more than 256 bytes data are sent to a device, the address counter rolls over within the same page, the previously latched data are di scarded, and the last 256 bytes data are kept to be programmed into the page. the starting byte can be anywhere within the page. when the end of the page is reached, the address will wrap around to the beginning of the same page. if the data to be programmed are less than a full page, the data of all other bytes on the same page will remain unchanged. note: a program operation can alter ?1?s into ?0?s, but an erase operation is required to change ?0?s back to ?1?s. a byte cannot be reprogrammed without first erasing the whole sector or block. figure 19. page program sequence
IS25WQ080 integrated silicon solution, inc.- www.issi.com rev. a 09/18/2012 29 device operation (continued) quad input page program operation the quad input page program instruction allows up to 256 bytes data to be programmed into memory in a single operation with four pins (io0, io1, io2 and io3). the destination of the memory to be programmed must be outside the protected memory area set by the block protection (bp3, bp2, bp1, bp0) bits. a quad input page program instruction which attempts to program into a page that is write- protected will be ignored. before the execution of quad input page program instruction, the qe bit in the status register must be set to ?1? and the write enable latch (wel) must be enabled through a write enable (wren) instruction. the quad input page program instruction code, three address bytes and program data (1 to 256 bytes) are input via the four pins (io0, io1, io2 and io3). program operation will start immediately after the ce# is brought high, otherwise the quad input page program instruction will not be executed. the internal control logic automatically handles the programming voltages and timing. during a program operation, all instructions will be ignored except the rdsr instruction. the progress or completion of the program operation can be determined by reading the wip bit in status register via a rdsr instruction. if the wip bit is ?1?, the pr ogram operation is still in progress. if wip bit is ?0?, the program operation has completed. if more than 256 bytes data are sent to a device, the address counter rolls over within the same page, the previously latched data are discarded, and the last 256 bytes data are kept to be programmed into the page. the starting byte can be anywhere within the page. when the end of the page is reached, the address will wrap around to the beginning of the same page. if the data to be programmed are less than a full page, the data of all other bytes on the same page will remain unchanged. note: a program operation can alter ?1?s into ?0?s, but an erase operation is required to change ?0?s back to ?1?s. a byte cannot be reprogrammed without first erasing the whole sector or block. figure 20. quad page program sequence 0 1 2345 67 8 9 10 11 28 29 30 31 ... instruction = 0101 0010b ... 23 22 21 3 2 1 0 3 - byte address ce# sck io0 io1 32 33 34 35 io2 io3 0 5 4 data in 2 2 7 6 data in 1 4 5 6 7 1 3 0 1 2 3 00110010 b
IS25WQ080 integrated silicon solution, inc.- www.issi.com rev. a 09/18/2012 30 device operation (continued) dual input page program operation the dual input page program instruction allows up to 256 bytes data to be programmed into memory in a single operation with two pins (io0, io1). the destination of the memory to be programmed must be outside the protected memory area set by the block protection (bp3, bp2, bp1, bp0) bits. a dual input page program instruction which attempts to program into a page that is write-protected will be ignored. before the execution of dual input page program instruction, the write enable latch (wel) must be enabled through a write enable (wren) instruction. the dual input page program instruction code, three address bytes and program data (1 to 256 bytes) are input via the two pins (io0, io1). program operation will start immediately after the ce# is brought high, otherwise the dual input page program instruction will not be executed. the internal control logic automatically handles the programming voltages and timing. during a program operation, all instructions will be ignored except t he rdsr instruction. the progress or completion of the program operation can be determined by reading the wip bit in status register via a rdsr instruction. if the wip bit is ?1?, the program operation is still in progress. if wip bit is ?0?, the program operation has completed. if more than 256 bytes data are sent to a device, the address counter rolls over within the same page, the previously latched data are discarded, and the last 256 bytes data are kept to be programmed into the page. the starting byte can be anywhere within the page. when the end of the page is reached, the address will wrap around to the beginning of the same page. if the data to be programmed are less than a full page, the data of all other bytes on the same page will remain unchanged. note: a program operation can alter ?1?s into ?0?s, but an erase operation is required to change ?0?s back to ?1?s. a byte cannot be reprogrammed without first erasing the whole sector or block.
IS25WQ080 integrated silicon solution, inc.- www.issi.com rev. a 09/18/2012 31 figure 21. dual input page program sequence 0 1 2345 67 8 9 10 11 28 29 30 31 ... instruction = 0101 0010b ... 23 22 21 3 2 1 0 3 - byte address ce# sck io0 io1 32 33 34 35 36 37 38 39 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 ce# sck io0 io1 data in 1 data in 2 io2 io3 data in n . . . io2 io3
IS25WQ080 integrated silicon solution, inc.- www.issi.com rev. a 09/18/2012 32 device operation (continued) erase operation the memory array of the IS25WQ080 is organized into uniform 4 kbyte sectors or 64 kbyte uniform blocks (a block consists of sixteen adjacent sectors). before a byte can be reprogrammed, the sector or block that contains the by te must be erased (erasing sets bits to ?1?). in order to erase the devices, there are three erase instructions available: sector erase (sector_er), block erase (block_er) and chip erase (chip_er). a sector erase operation allows any individual sector to be erased without affecting the data in other sectors. a block erase operation erases any individual block. a chip erase operation erases the whole memory array of a devic e. a sector erase, block erase or chip erase operation can be executed prior to any programming operation. sector_er command (sector erase) operation a sector_er instruction erases a 4 kbyte sector before the execution of a sector_er instruction, the write enable latch (wel) must be set via a write enable (wren) instruction. the wel bit is reset automatically after the comp letion of sector an erase operation. a sector_er instruction is entered, after ce# is pulled low to select the device and stays low during the entire instruction sequence the sector_er instruction code, and three address bytes are input via si. erase operation will start immediately after ce# is pulled high. the internal control logic automatically handles the erase voltage and timing. refer to figure 22 for sector erase sequence. during an erase operation, all instruction will be ignored except the read status register (rdsr) instruction. the progress or completion of the erase operation can be determined by reading the wip bit in the status register using a rdsr instruction. if the wip bit is ?1?, the erase oper ation is still in progress. if the wip bit is ?0?, t he erase operation has been completed. block_er command (block erase) operation a block erase (block_er) instruction erases a 32k/64 kbyte block of t he IS25WQ080. before the execution of a block_er instruction, the write enable latch (wel) must be set via a write enable (wren) instruction. the we l is reset automatically after the completion of a block erase operation. the block_er instruction code and three address bytes are input via si. er ase operation will start immediately after the ce# is pulled high, otherwise the block_er instruction will not be executed. the internal control logic automatically handles the erase voltage and timing. refer to figure 23 for block erase sequence. chip_er command (chip erase) operation a chip erase (chip_er) instruction erases the entire memory array of a IS25WQ080. before the execution of chip_er instruction, the write enable latch (wel) must be set via a write enable (wren) instruction. the wel is reset automatically after completion of a chip erase operation. the chip_er instruction code is input via the si. erase operation will start immediately after ce# is pulled high, otherwise the chip_er instruction will not be executed. the internal c ontrol logic automatically handles the erase voltage and timing. refer to figure 24 for chip erase sequence.
IS25WQ080 integrated silicon solution, inc.- www.issi.com rev. a 09/18/2012 33 device operation (continued) figure 22. sector erase sequence figure 23. block erase sequence figure 24. chip erase sequence
IS25WQ080 integrated silicon solution, inc.- www.issi.com rev. a 09/18/2012 34 device operation (continued) deep power down the power-down (dp) instruction is for setting the device on the minimizing the power consumption (enter into power-down mode), the standby current is reduced from isb1 to isb2). during the power-down mode, the device is not active and all write/program/erase instruction are ignored. the instruction is initiated by driving the ce# pin low and shifting the instruction code ?b9h? as show in the figure 25. the ce# pin must be driven high after the instruction has been latched. if this is not done the power-down will not be ex ecuted. after ce# pin driven high, the power-down state will entered within the time duration of t dpd . while in the power-down state only the release from power-down / rdid instruction, which restores the device to normal operation, will be recognized. all other instructions are ignored. this includes the read status register instruction, which is always available during normal operation. ignoring all but one instruction makes the power down state a useful condition for securing maximum write protection. figure 25. power down sequence figure 26. release power down sequence
IS25WQ080 integrated silicon solution, inc.- www.issi.com rev. a 09/18/2012 35 device operation (continued) program security information row instruction (psir) the psir instructions can read and programmed (erase) using three dedicated instructions. the program information raw instruction is used to program at most 256 bytes to the security memory area (by changing bits from ?1? to ?0?, only). before it can be accepted, a write enable (wren) instruction must previously have been executed. after the write enable (wren) instruction has been decoded, the device sets the write enable latch (wel) bit. the program information row instruction is entered by driving ce# pin low, followed by the instruction code, three address bytes and at least one data byte on serial data input (si). ce# pin must be driven high after the eighth bits of the last data byte has been latched in, otherwise the program information row instruction is not executed. if more than 256 bytes data are sent to a device, the address counter can not roll over. after ce# pin is driven high, the self-timed page program cycle (whose duration is t potp ) is initiated. while the program otp cycle is in progress, the status register may be read to check the value of the write in progress (wip) bit. the write in progress (wip) bit is 1 during the self-timed program cycle, and it is 0 when it is completed. at some unspecified time before the cycle is complete, the write enable latch (wel) bit is reset. figure 27. program information raw sequence note: 1 ? n ? 256 note: 1. the sir address is from 000000h to 0000ffh. 2. the sir protection bit is in the address 000100h
IS25WQ080 integrated silicon solution, inc.- www.issi.com rev. a 09/18/2012 36 device operation (continued) to lock the otp memory: bit 0 of the otp control byte, that is byte256, is used to permanently lock the otp memory array. when bit 0 of byte 256 = ?1?, the 256 bytes of the otp memory array can be programmed. when bit 0 of byte 256 = ?0?, the 256 bytes of the otp memory array are read-only and cannot be programmed anymore. once a bit of the otp memory has been programmed to ?0?, it can no longer be set to ?1?. therefore, as soon as bit 0 of byte 256 (control byte) is set to ?0?, the 256 bytes of the otp memory array become read-only in a permanent way. any program otp (potp) instruction issued while an erase, program or write cycle is in progress is rejected without having any effect on the cycle that is in progress figure 28. otp area
IS25WQ080 integrated silicon solution, inc.- www.issi.com rev. a 09/18/2012 37 device operation (continued) read security information row (rsir) the rsir instruction read the security information row. there is no rollover mechanism with the read otp (rotp) instruction. this means that the read otp (rotp) instruction must be sent with a maximum of 256 bytes to read, since once the 256 th byte has been read, the same (256 th ) byte keeps being read on the so pin. fig 29. read security information row instruction
IS25WQ080 integrated silicon solution, inc.- www.issi.com rev. a 09/18/2012 38 device operation (continued) program/erase suspend resume the device allow the interr uption of sector-erase, block-erase or page-program operations and conduct other operations. to enter the suspend/ resume mode: issuing 75h/b0h for suspend; 7ah/30h for resume read function register bit2 (psus) and bit1 (esus) to check suspend ready information. suspend to suspend ready timing: 20us. resume to another suspend timing: 1ms. *note: it needs 500ns delay time from write command to suspend command program/erase suspend during sector-erase or block-erase after erase suspend, wel bit will be clear, only read related, resume and reset command can be accepted. (03h, 0bh, bbh, ebh, 05h, abh, 9fh, 90h, 4bh) to execute a program/eras e suspend operation, the host drives ce# low, sends the program/erase suspend command cycle (75h/b0h), then drives ce# high. the function register indicates that the erase has been suspended by changing the esus bit from ?0? to ?1,? but the device will not accept another command until it is ready. to determine when the device will accept a new command, poll the wip bit in the status register or wait t ws . when esus bit is issued, the write enable latch (wel) bit will be reset. program/erase suspend during page programming program suspend allows the interruption of all program operations. after program suspend, we l bit will be cleared, only read related, resume and reset command can be accepted. ( 03h, 0bh, bbh, ebh, 05h, abh, 9fh, 90h, 4bh) to execute a program/eras e suspend operation, the host drives ce# low, sends the program/erase suspend command cycle (75h/b0h), then drives ce# high. the function register indicates that the programming has been suspended by changing the psus bit from ?0? to ?1,? but the device will not accept another command until it is ready. to determine when the device will accept a new command, poll the wip bit in the status register or wait t ws . program/erase resume program/erase resume restarts a program/erase command that was suspended, and changes the suspend status bit in the ( esus or psus) back to ?0?. to execute a program/eras e resume operation, the host drives ce# low, sends the program/erase resume command cycle (7ah/30h), then drives ce# high. to determine if the internal, self-timed write operation completed, poll the wip bit in the status register, or wait the specified time t se , t be or t pp for sector- erase, block-erase, or page-programming, respectively. the total write time before suspend and after resume will not exc eed the uninterrupted write times t se , t be or t pp .
IS25WQ080 integrated silicon solution, inc.- www.issi.com rev. a 09/18/2012 39 device operation (continued ) rdfr command (read function register) operation the read function register (rdfr) instruction provides access to the erase/program suspend register. during the execution of a program, erase or write status register suspend, which can be used to check the suspend status. figure 30. read function register sequence absolute maximum ratings (1) storage temperature -65 o c to +150 o c surface mount lead soldering temperature standard package 240 o c 3 seconds lead-free package 260 o c 3 seconds input voltage with respect to ground on all pins (2) -0.5 v to vcc + 0.5 v all output voltage with respect to ground -0.5 v to vcc + 0.5 v vcc (2) -0.5 v to +4.0 v notes: 1. applied conditions greater than those listed in ?abs olute maximum ratings? may cause permanent damage to the device. this is a stress rating only. the functional operation of the device condi tions that exceed those indicated in the operational sections of this specific ation is not implied. exposure to absolute maximum rating condition for extended periods may affect device reliability. 2. maximum dc voltage on input or i/o pins is v cc + 0.5 v. during voltage transitions, input or i/o pins may overshoot v cc by + 2.0 v for a period of time not to exceed 20 ns. minimum dc voltage on input or i/o pins is -0.5 v. during voltage transitions, input or i/o pins may undershoot gnd by -2.0 v for a period of time not to exceed 20 ns. 0000 0111
IS25WQ080 integrated silicon solution, inc.- www.issi.com rev. a 09/18/2012 40 dc and ac operating range part number IS25WQ080 operating temperature (extended grade) -40 o c to 105 o c operating temperature (i ndustrial grade) -40 o c to 85 o c operating temperature (aut omotive, a1 grade) -40 o c to 85 o c operating temperature (aut omotive, a2 grade) -40 o c to 105 o c operating temperature (aut omotive, a3 grade) -40 o c to 125 o c vcc power supply 1.65 v ?2.0 v dc characteristics applicable over recommended operating range from: v cc = 1.65 v to 2.0 v (unless otherwise noted). symbo parameter condition min ty p max units i cc1 vcc active read current v cc = 2.0 v at 33 mhz, so = open 10 15 ma i cc2 vcc program/erase current v cc = 2.0 v at 33 mhz, so = open 15 20 ma i sb1 vcc standby current cmos v cc = 2.0 v, ce# = v cc 50 ? a i sb2 vcc standby current ttl v cc = 2.0 v, ce# = v ih to v cc 3 ma i li input leakage current v in = 0v to v cc 1 ? a i lo output leakage current v in = 0v to v cc , t ac = 0 o c to 130 o c 1 ? a v il input low voltage -0.5 0.3vcc v v ih input high voltage 0.7v cc v cc + 0.4 v v ol output low voltage 1.65v < v cc < 2.0 v i ol = 100 ? a 0.2 v v oh output high voltage i oh = -100 ? a v cc ? 0.2 v
IS25WQ080 integrated silicon solution, inc.- www.issi.com rev. a 09/18/2012 41 ac characteristics applicable over recommended operating range from v cc = 1.65 v to 2.0 v c l = 1 ttl gate and 30 pf (unless otherwise noted). symbol parameter min typ max units f ct clock frequency for fast read mode 0 104 mhz f c clock frequency for read mode 0 33 mhz t ri input rise time 8 ns t fi input fall time 8 ns t ckh sck high time 4 ns t ckl sck low time 4 ns t ceh ce# high time 25 ns t cs ce# setup time 10 ns t ch ce# hold time 5 ns t ds data in setup time 2 ns t dh data in hold time 2 ns t hs hold setup time 15 ns t hd hold time 15 ns t v output valid 8 ns t oh output hold time normal mode 0 ns t lz hold to output low z 200 ns t hz hold to output high z 200 ns t dis output disable time 100 ns t ec sector erase time 70 150 ms block erase time (32kb) 0.12 0.5 s block erase time(64kb) 0.15 0.5 s chip erase time (8mb) 2 5 s chip erase time (16mb) 5 12 s t pp page program time 0.6 0.7 ms t vcs v cc set-up time 50 ? s t res1 release deep power down 10 ? s ? t dp deep power down 10 ? s ? t w write status register time 10 15 ms ? tsus suspend to suspend ready 20 us trs resume to another suspend 1 ms tsrst software reset cover time 15 ms tws suspend time 20 us
IS25WQ080 integrated silicon solution, inc.- www.issi.com rev. a 09/18/2012 42 ac characteristics (continued) serial input/output timing (1) note: 1. for spi mode 0 (0,0)
IS25WQ080 integrated silicon solution, inc.- www.issi.com rev. a 09/18/2012 43 ac characteristics (continued) hold timing pin capacitance (f = 1 mhz, t = 25c ) typ max units conditions c in 4 6 pf v in = 0 v c out 8 12 pf v out = 0 v note: these parameters are charac terized but not 100% tested. output test load input test waveforms and measurement level 30pf
IS25WQ080 integrated silicon solution, inc.- www.issi.com rev. a 09/18/2012 44 power-up and power-down at power-up and power-down, the device must not be selected (ce# must follow the voltage applied on vcc) until vcc reaches the correct value: 1. vcc(min) at power-up, and then for a further delay of tvce 0 vss at power-down usually a simple pull-up resistor on ce# can be used to insure safe and proper power-up and power-down. to avoid data corruption and inadvertent write operations during power up, a power on reset (por) circuit is included. the logic inside the device is held reset while vcc is less than the por threshold value (vwi) during power up, the device does not respond to any instruction until a time delay of tpuw has elapsed after the moment that vcc rised above the vwi threshold. however, the corre ct operation of the device is not guaranteed if, by this time, vcc is still below vcc(min). no write status register, program or erase instructions should be sent until the later of: - tpuw after vcc passed the vwi threshold - tvce after vcc passed the vcc(min) level at power-up, the device is in the following state: - the device is in the standby mode - the write enable latch (wel) bit is reset at power-down, when vcc drops from the operating voltage, to below the vwi, all write operations are disabled and the device does not respond to any write instruction. chip selection not allowed all write commands are rejected tvce read access allowed device fully accessible tpuw vcc vcc(max) vcc(min) reset state v (write inhibit) time symbol parameter min. max. unit t vce *1 vcc(min) to ce# low 10 us t puw *1 power-up time delay to write instruction 1 10 ms v wi *1 write inhibit voltage 2.4 v note : *1. these parameters are characterized only. 1.3
IS25WQ080 integrated silicon solution, inc.- www.issi.com rev. a 09/18/2012 45 program/erase performance parameter unit typ max remarks sector erase time ms 70 150 from writing erase command to erase completion block erase time s 0.15 0.5 from writing erase command to erase completion chip erase time (16mb) s 5 12 from writing erase command to erase completion chip erase time (8mb) s 2 6 from writing erase command to erase completion page programming time ms 0.6 0.7 from writing program command to program completion byte program us 8 25 first byte additional byte program us 2.5 12 after first byte note: these parameters are characterized and are not 100% tested. reliability characteristics parameter min typ unit test method endurance 100,000 cycles jedec standard a117 data retention 20 years jedec standard a103 esd ? human body model 2,000 volts jedec standard a114 esd ? machine model 200 volts jedec standard a115 latch-up 100 + i cc1 ma jedec standard 78 note: these parameters are characterized and are not 100% tested.
IS25WQ080 integrated silicon solution, inc.- www.issi.com rev. a 09/18/2012 46 package type information ` jn 8-pin jedec 150mil broad small outlin e integrated circuit (soic) package (measure in millimeters)
IS25WQ080 integrated silicon solution, inc.- www.issi.com rev. a 09/18/2012 47 package type information (continued) ` jb 8-pin jedec 208mil broad small outlin e integrated circuit (soic) package (measure in millimeters)
IS25WQ080 integrated silicon solution, inc.- www.issi.com rev. a 09/18/2012 48 package type information (continued) jp 8-contact ulta-thin small ou tline no-lead (wson) package (measure in millimeters)
IS25WQ080 integrated silicon solution, inc.- www.issi.com rev. a 09/18/2012 49 package type information (continued) ja 8-pin 300mil wide body, plastic dual in-lin e package pdip (measure in millimeters)
IS25WQ080 integrated silicon solution, inc.- www.issi.com rev. a 09/18/2012 50 package type information (continued) jm 16 pin -- - 16-lead plastic small outline, 300 mils body width, package outline 1.27 0.51 0.33 2.4 2.25 2.35 2.65 0.1 8 0 0 0 1.27 0.4 detail a detail a 0.23 millimeters 18 9 16 10.5 10.1 7.4 7.6 10.0 10.65 0.32 0.1 0.3
IS25WQ080 integrated silicon solution, inc.- www.issi.com rev. a 09/18/2012 51 package type information (continued) jv 8-pin vvsop 150mil
IS25WQ080 integrated silicon solution, inc.- www.issi.com rev. a 09/18/2012 52
IS25WQ080 integrated silicon solution, inc.- www.issi.com rev. a 09/18/2012 53 appendix1: safe guard function safe guard function is a security function fo r customer to protect by sector (4kbyte). every sector has one bit register to decide it will unde r safe guard protect or not. (?0?means protect and ?1? means not protect by safe guard.) IS25WQ080 (secto r 0~sector 255). is25wq016 (sector 0~sector 511) mapping table for safe guard register address d7 d6 d5 d4 d3 d2 d1 d0 sector0 000h 1 1 1 1 1 1 1 0 sector1 000h 1 1 1 1 1 1 0 1 sector2 000h 1 1 1 1 1 0 1 1 sector3 000h 1 1 1 1 0 1 1 1 sector4 000h 1 1 1 0 1 1 1 1 sector5 000h 1 1 0 1 1 1 1 1 sector6 000h 1 0 1 1 1 1 1 1 sector7 000h 0 1 1 1 1 1 1 1 sector8 001h 1 1 1 1 1 1 1 0 sector9 001h 1 1 1 1 1 1 0 1 sector10 001h 1 1 1 1 1 0 1 1 sector11 001h 1 1 1 1 0 1 1 1 sector12 001h 1 1 1 0 1 1 1 1 sector13 001h 1 1 0 1 1 1 1 1 sector14 001h 1 0 1 1 1 1 1 1 sector15 001h 0 1 1 1 1 1 1 1 ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? sector248 01fh 1 1 1 1 1 1 1 0 sector249 01fh 1 1 1 1 1 1 0 1 sector250 01fh 1 1 1 1 1 0 1 1 sector251 01fh 1 1 1 1 0 1 1 1 sector252 01fh 1 1 1 0 1 1 1 1 sector253 01fh 1 1 0 1 1 1 1 1 sector254 01fh 1 0 1 1 1 1 1 1 sector255 01fh 0 1 1 1 1 1 1 1
IS25WQ080 integrated silicon solution, inc.- www.issi.com rev. a 09/18/2012 54 read safe guard register the read safe guard instruction code is transmitted via the slo line, followed by three address bytes (a23 ? a0) of the first register location to be read. the first byte data (d7 ? d0) addressed is then shifted out on the so line, msb first. the address is automatically incremented after each byte of data is shifted out. the read operation can be terminated at any time by driving ce# high (v ih ) after the data comes out. fig a. timing waveform of read safe guard register erase safe guard register if we want to erase the safe guard register to let the flash into unprotect status, it needs five continuous instructions. if any instruction is wrong, the erase comm and will be ignored. erase wait time follow product erase timing spec. fig b. shows the complete steps for erase safe guard register. program safe guard register if we want to erase the safe guard register to let the flash into unprotect status, it needs five continuous instructions. if any instruction is wron g, the program command will be ignored. the program safe guard instruction allows up to 256 bytes data to be programmed into memory in a single operation. program wait time follow product program timing spec. fig c. shows the complete steps for program safe guard register. cs sck si 12 78 2fh 910 2324 a23-a0 25 26 31 32 d7-d0 d7-d0 33 34 39 40 so 41 42 47 48 1 s t by te 2 n d by te
IS25WQ080 integrated silicon solution, inc.- www.issi.com rev. a 09/18/2012 55 fig b. erase safe guard register
IS25WQ080 integrated silicon solution, inc.- www.issi.com rev. a 09/18/2012 56 fig c. program safe guard register 1 s t byte 2nd b y te
IS25WQ080 integrated silicon solution, inc.- www.issi.com rev. a 09/18/2012 57 appendix2: sector unlock function instruction name hex code operation command cycle maximum frequency sect_unlock 26h sector unlock 4 bytes 104 mhz sect_lock 24h sector lock 1 byte 104 mhz sec_unlock command operation the sector unlock command allows the user to select a specific sector to allow program and erase operations. this instruct ion is effective when the blocks are designated as write-protected through the bp0, bp1, bp2 and bp3 bits in the status register. only one sector can be enabled at any time. to enable a different sector, a previously enabled sector must be disabled by executing a sector lock command. the instruction code is followed by a 24-bit address specifying the target sector, but a0 through a11 are not decoded. the remaining sectors within the same block remain in read-only mode. figure d. sector unlock sequence note: 1.if the clock number will not match 8 clocks(c ommand)+ 24 clocks (add ress), it will be ignored. 2.it must be executed write enabl e (06h) before sector unlock instructions.
IS25WQ080 integrated silicon solution, inc.- www.issi.com rev. a 09/18/2012 58 sect_lock command operation the sector lock command reverses the function of the sector unlock command. the instruction code does not require an address to be specified, as only one sector can be enabled at a time. the remaining sectors within the same block remain in read-only mode. figure e. sector lock sequence
IS25WQ080 integrated silicon solution, inc.- www.issi.com rev. a 09/18/2012 59 product ordering information is25wq*** - ja l e temperature range e = extended grade (-40c to +105c) i = industrial grade (-40c to +85c) a1 = automotive, a1 gr ade (-40c to +85c) a2 = automotive, a2 grade (-40c to +105c) a3 = automotive, a3 grade (-40c to +125c) environmental attribute l = lead-free (pb-free) package package type ja = 8-pin pdip jb = 8-pin soic 208 mil jp = 8-contact wson jm =16-pin soic 300mil jn = 8-pin soic 150 mil jv = 8-pin vvsop 150 mil device number IS25WQ080
IS25WQ080 integrated silicon solution, inc.- www.issi.com rev. a 09/18/2012 60 ordering information: density frequency (mhz) order part number package 8m 104 IS25WQ080-jale 8-pin pdip 300mil IS25WQ080-jble 8-pin soic 208-mil IS25WQ080-jple 8-pin wson IS25WQ080-jmle 16-pin soic 300-mil IS25WQ080-jnle 8-pin soic 150mil IS25WQ080-jvle 8-pin vvsop 150-mil IS25WQ080-jali 8-pin pdip 300mil IS25WQ080-jbli 8-pin soic 208-mil IS25WQ080-jpli 8-pin wson IS25WQ080-jmli 16-pin soic 300-mil IS25WQ080-jnli 8-pin soic 150mil IS25WQ080-jvli 8-pin vvsop 150-mil IS25WQ080-jala1 8-pin pdip 300mil IS25WQ080-jbla1 8-pin soic 208-mil IS25WQ080-jpla1 8-pin wson IS25WQ080-jmla1 16-pin soic 300-mil IS25WQ080-jnla1 8-pin soic 150mil IS25WQ080-jvla1 8-pin vvsop 150-mil IS25WQ080-jala2 8-pin pdip 300mil IS25WQ080-jbla2 8-pin soic 208-mil IS25WQ080-jpla2 8-pin wson IS25WQ080-jmla2 16-pin soic 300-mil IS25WQ080-jnla2 8-pin soic 150mil IS25WQ080-jvla2 8-pin vvsop 150-mil

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